Abstract
Dual-core microprocessors are currently the center of attention in computing design. There is a definite shift away from ever higher frequencies to multicore processors to meet higher-performance requirements without pushing power consumption beyond what can be tolerated in many applications. It’s not just about a drastic improvement in the speed of different applications, but a completely new digital experience. Employing virtualization technology to share a single CPU platform between Windows and an RTOS performs well for a large number of real-time Windows applications. Typically, applications with cycle times of one millisecond or slower are served quite well by this arrangement and have been deployed on standard desktop and industrial motherboard platforms (e.g., single-core Intel Pentium 4 and Celeron processors running at speeds of 1-3GHz). There are some applications which demand even faster cycle times; the availability of dual-core processors can improve real-time cycle times by an order of magnitude. When virtual machines share a single-core CPU they must maintain a full machine context (or a partial context in the case of a hyper-threaded core) to switch between the two operating systems. Saving and restoring these contexts results in overhead that affects latencies and minimum cycle times. The overhead can contribute 10 to 30 microseconds to event latency. For cycle times of one millisecond or slower, 10-30 microseconds of latency represents a jitter variation of only a few percent.
When applied to a dual-core processor, this technology can dedicate one CPU core to the RTOS; meaning the instruction cycles of the dedicated core are available 100% of the time to the RTOS and its processes. All remaining CPU cores are dedicated to the Windows virtual machine. Contention for key CPU resources such as pipelines, cache, and the FPU are avoided. Coordination between the two virtual machines is enhanced by using the built-in interprocessor communication mechanisms, completely eliminating context switch times.
In a dedicated multi-core configuration, real-time event latencies are reduced by an order of magnitude over single-core hardware, to as low as 1-3 microseconds. Cycle times of 50-200 microseconds are possible for very precise and accurate control loops.
This seminar attempts to peep in this technology and tries to explain the need for evolution for such a technique and the alternative paths that have been followed since. It also surmises the advantages and disadvantages of using such systems.
Keywords-Tlp(Thread Level Prallelism),CLM(Chip Level Multiprocessing),Multicore,SymmertricMulti Processing(SMP),Hyperthreading, Multiprocessing,Simulatneous Multithreading(SMT), Multitasking,
…………….So on ..........(download any of the following links to get complete paper presentation in word document)
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