Sunday, February 22, 2009

DATA COMPACTION IN VLSI CIRCUITS USING PARITY BIT SIGNATURE .doc (Paper Presentation)

ABSTRACT

The design of efficient time compression support hardware for built in self testing (BIST) is of great importance in the design and manufacturing of VLSI circuits. The diagnostic technology of digital systems have progressed from the state of testing the operation codes of the machine instruction set early days to current hardware asserts with software aid for speedy determinations identification of faulty elements. In VLSI the diagnosis is shifted from locating the faulty discrete components in the circuits. The fault is the physical defect in the circuit; As the VLSI systems are becoming more and more complex the fault diagnosis and testing the digital circuits become trivial in the manufacturing process. Fault diagnosis consists of two parts they are fault location and fault detection. Fault detection is the determination of faults which may include single and multiple faults that have occurred .The process of apply tests and determining whether digital circuits is fault free or not is generally called


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