45-NANOMETER GENERATION .doc (Abstract)

45-NANOMETER GENERATION

-NO MORE CAKEWALK IN INTEGRATED CIRCUIT RESERCH

ABSTRACT:

A welcome development but hardly big news! After all, the density of transistors on chips has been periodically doubling, as predicted by Moore’s law, for more than 40 years. The smallest parts of the transistor has to be diminished, but there’s one part which couldn’t been slimmed and shrunk ie., silicon dioxide insulation that electrically isolates the transistors gate from the channel through which the current flows when the transistor is on. The solution led to a new breakthrough in the semiconductor industry ie., “high k dielectric plus metallic gate transistor”(reducing leakage current into the gate terminal). The paper depicts why the insulation layer and gate of conventional transistors are replaced by high-k dielectric insulation layer and metallic gate electrode instead poly crystalline silicon. The paper also describes about uneven surface dielectric charges, phonons scatter electrons in channel, poor bonding between gate and dielectric which makes transistor hard to turn on. It also tells about “Fermi level pinning” and fabrication methods of High K+MG Transistors. Finally the paper concludes how this becomes the basis for 32 nm. 22nm, 16nm transistors in the future.