ABSTRACT:
This paper provides the experience of applying an advanced version of our former spurious power suppression technique (SPST) on multipliers for high –speed and low- power purposes. To filter out the useless switching power , there are two approaches i.e., using registers and using AND gates, to assert signals of multipliers after the data transition .The SPST has been applied on both the modified booth encoder and the compression tree of multiplier to enlarge the data transition .the simulation show that the SPST implementation with the AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a
40% speed improvement .adopting a 0.18-µm CMOS technology, the proposed SPST equipped multiplier dissipates only 0.0121 m W per MHz in
…………….So on ..........(download any of the following links to get complete paper presentation in word document)
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